The disclosures herein relate generally to ground bounce caused by simultaneous switching of I/O buffers in complex integrated circuits and, more particularly, to a ground bounce prediction methodology and use thereof in data error reduction.
Simultaneous switching of I/O buffers in complex integrated circuits create sudden shifts in the ground and power plane voltages. These shifts, generically referred to as xe2x80x9cground bounce,xe2x80x9d cause relative shifts in the output buffers"" signals to the extent that a xe2x80x9c0xe2x80x9d can be detected as a xe2x80x9c1xe2x80x9d and vice versa, causing data errors. This problem is becoming increasingly troublesome due to lowered signal voltage levels and their consequent lower noise margins and the increase in density of I/O in increasingly complex chips. The worst ground bounce scenarios occur when most or all I/O buffers drive their output simultaneously.
Prior methods of addressing the above-described problem include adjusting the slew rate of individual I/O buffers, increasing the interplane capacitance using on-chip capacitors, and increasing the decoupling in the immediate region of the transmitting chip. These prior art solutions suggest the use of long phase delay periods on the order of the ground bounce resonance period, but do not include phase de-skewing and are therefore not exceedingly practical without a major revision of bus timing and protocol. They also fail to provide a methodology for predicting ground bounce and for using this prediction information in reducing data error.
Therefore, what is needed is a ground bounce prediction methodology and use thereof in data error reduction.
One embodiment, accordingly, is a methodology for predicting incidents of ground bounce and using this information for reducing data error caused thereby. In particular, data to be clocked into a plurality of output buffers from a first register is read before it goes to the buffers and a determination is made as to what number of bits B will change state, i.e., from a zero to a one or a one to a zero. B is then compared to a predetermined threshold T. If B is greater than T, a wait state or some other indication will be issued when the bits are clocked into the I/O buffers.
A principal advantage of the embodiment is that ground bounce can be predicted prior to its occurrence and steps taken to reduce data error caused thereby.